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CDCLVP111-EP: |Vih – Vil| clarification

Michael T Schneider
Expert 3780 points
Part Number: CDCLVP111-EP
Other Parts Discussed in Thread: LMK00338, CDCLVP111-SP

On the CDCLVP111-ep datasheet again, Is |Vih – Vil| = 0.5V min on p.6 of the datasheet for peak-to-peak of Vid?

|Vih – Vil| may have DC offset in it – see below figure (ref LMK00338 datasheet), where Vid has DC offset. I wonder if the |Vih – Vil| = 0.5V min for CDCLVP111-EP has DC offset. For AC-coupled input, I wonder what’s the peak-to-peak min spec. 

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    TI__Genius 14540 points
    Hi Michael,
    I'm not sure I understand the question. Here is my understanding of the CDCLVP111-SP spec.

    Each clock input, CLKP and CLKN, must have a signal whose voltage difference from high level to level is between 0.5V and 1.3V. Any common mode offset on these pins will not affect the difference in these voltages.

    Thanks
    Christian