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TMS320C6678: 【DSP: TMS320C6678 & tms320tci6608】what is the VIH/VIL of CORECLK, DDRCLK, PCIECLK？ how to affirm the waveform are OK？thanks！！

user5300760
Prodigy 40 points
Part Number: TMS320C6678
Other Parts Discussed in Thread: TMS320TCI6608

we read the datasheet and have questions，especially about the Standard of measurement of the signal  CORECLKP、CORECLKN、DDRCLKP、DDRCLKN、PCIECLKP、PCIECLKN

take TMS320C6678 as examle，with the datasheet  《TMS320C6678SPRS691D—April 2013   Multicore Fixed and Floating-Point Digital Signal Processor  SPRS691D—April 2013》

1、page 116、117，what is the VIH/VIL/swing/common-mode voltage  of LVDS/LJCB？

Input voltage (VI) range:

All differential clock inputs comply with the LVDS Electrical Specification, IEEE 1596.3-1996 and all SERDES I/Os comply with the XAUI Electrical Specification, IEEE 802.3ae-2002.

2、what is the VIH/VIL/swing/common-mode voltage   of CORECLKP、CORECLKN、DDRCLKP、DDRCLKN、PCIECLKP、PCIECLKN？

we should pay atention to Differential signal or single ended signal.？ and what parameter  we should measure the signal？

we look forward to your early reply！

  • 0
    Prodigy 40 points
    We are expecting your prompt reply！Thanks very much！
  • 0
    TI__Guru**** 161600 points
    Hi,

    As said in the datasheet, you can find this information VIH/VIL/swing/common-mode voltage in the LVDS Electrical Specification.

    Some information, to which I have access is available here:
    www.ti.com/.../technical-documents.html

    For PCIE clk (which uses serdes) you should refer to the following recommendation: "IEEE 1596.3-1996 and all SERDES I/Os comply with the XAUI Electrical Specification, IEEE 802.3ae-2002."


    Best Regards,
    Yordan
  • 0 in reply to user5300760
    Prodigy 40 points
    THANK U for so many handbooks！

    then，can you give me the exact value of VIH/VIL/swing/common-mode voltage ？
    just about these signal？——CORECLKP、CORECLKN、DDRCLKP、DDRCLKN、PCIECLKP、PCIECLKN
    （TMS320TCI6608, TMS320C6678）
  • 0 in reply to Yordan Kovachev
    TI__Mastermind 25566 points

    Yordan Kovachev said:
    As said in the datasheet, you can find this information VIH/VIL/swing/common-mode voltage in the LVDS Electrical Specification.

    Do you mean this data  of VIH and VIL?

    But seems clock belong to LJCB power domain.

    and LJCB power level is:<1.3V

    Refer application notes sprabi4, clocking design guide for keystone device , which item should we follow?

    According to SPRABL2C: Hardware Design Guide for KeyStone I devices page 82, keysone clock input are LJCB, need AC coupling, but we can't find driver in data manual.

    please clarify VIH and VIL for LJCB buffer.

  • 0 in reply to Yordan Kovachev
    Prodigy 40 points
    Yordan Kovachev:
    can you give me the exact value of VIH/VIL/swing/common-mode voltage ？
    just about these signal？——CORECLKP、CORECLKN、DDRCLKP、DDRCLKN、PCIECLKP、PCIECLKN

    as tony tang described below,we need the exact value
  • 0 in reply to Tony Tang
    TI__Guru**** 161600 points
    Hi Tony,

    See this thread:
    e2e.ti.com/.../312730
    It discusses similar issue and should answer your questions.

    The Hardware design guide (www.ti.com/.../sprabi2c.pdf) states:
    "Low voltage differential swing LVDS and LVPECL clock sources are compatible with the LJCBs."
    See Section 3.1 System PLL Clock Inputs.

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    TI__Mastermind 46460 points

    Tony,

    The LJCB input buffer provides the required DC bias (and termination) for proper operation.  As such, series capacitors are required.  The VIL and VIH specifications are DC specifications and they are not relevant for board validation.  The relevant specifications are shown in Figures 7-21 and 7-22 on page 152 of the C6678 DM shown below:

    The only DC spec that is relevant is the single-ended Absolute Maximum Ratings shown in Table 6-1 on page 116.  The single-ended voltage on either the P or N clock pin must never be beyond the voltage range provided: LJCB: -0.3 V to 1.3 V.

    Tom

  • 0 in reply to Tom Johnson 16214
    TI__Expert 4586 points

    Hi Tom and Yordan,

    Thanks for reply. I would like to double confirm below points to directly answer customer's question:

    1 As LJCB input buffer includes DC bias and termination, so the input clock signal should be AC coupling input, and as it is AC source input, so there is no Vih and Vil spec. Right?

    2  In customer's case, the clock input is LVDS differential signal(P/N).  For swing question, it should follow up figure 7-22, peak to peak range is 250mv to 2V, which means the input clock for P or N absolute value should be in the range between -125mv/+125mv and -1V/+1V as it is AC source input. Right?

    If yes, according to Figure 7-22 title info, it is for CORE CLOCK and PCIE CLOCK, how about DDR3 CLCOK transition time? In Figure 7-24, there is DDR3 PLL DDRCLK Timing just like 7-21, but there is no DDR3 clock input transition time figure like 7-22.

    3  You mentioned  "The single-ended voltage on either the P or N clock pin must never be beyond the voltage range provided: LJCB: -0.3 V to 1.3 V", this is just for single-end clock source, right? If the input is differential clock, the input clock  just needs follow up Figure 7-21/Figure 7-22 and don't needs input as -0.3V to 1.3V. Right?

    4 Vih and Vil below are all for  DC source input, we don't need to care this if AC source input used, right?

    Thanks very much for your support!

  • 0 in reply to Thomas Yang55737
    TI__Mastermind 46460 points
    Thomas,

    1. Correct.

    2. It is assumed that the P and N signals are opposite and equal. However, the signal levels are not specified single-ended. The specification, as shown in figure 7-22, is a differential requirement. This is true for both level and transition time per the figure.

    3. Do not mix differential and single ended numbers when looking at the requirements. This leads to errors due to assumptions. The absolute maximum levels are single-ended measurements.

    4. The numbers in this table define the limits for the different types of LVDS. It lists the standards and their relative levels. As such, this document is a generic reference. The Data Manual has precedence and provides the specific requirements for the 66AK2Hxx device.

    Tom